用verilog编写一个全加器，实现4位串行加法器

module full_adder(input [3:0] a, input b, input carry_in, output [3:0] sum, output carry_out);
    assign {sum, carry_out} = a + b + carry_in;
endmodule

module serial_adder(input [3:0] a, input [3:0] b, output [3:0] sum);
    reg [3:0] carry_in;
    reg [3:0] temp_sum;

    generate
        for (integer i = 0; i < 4; i = i + 1) begin : GEN
            assign temp_sum[i] = a[i] ^ b[i] ^ carry_in[i];
            if (a[i] & b[i]) begin
                assign carry_in[i] = 1;
            end else if (a[i] | b[i]) begin
                assign carry_in[i] = carry_in[i - 1];
            end else begin
                assign carry_in[i] = 0;
            end
        end
    endgenerate

    assign sum = temp_sum;
endmodule